Code:
'**********************************************************************
'* Name : 18F26K22.BAS *
'* Author : [Leonardo Bilalis] *
'* Notice : Copyright (c) 2018 [Leonardo Bilalis] *
'* : All Rights Reserved *
'* Date : 30/Jun/2018 *
'* Version : 1.0 *
'* Notes : This is a GPS Tracker based on the following components *
'* : PIC18F26K22 or PIC18F46K22 @ 64Mhz *
'* : MKT 3333 or 3339 GPS MODULE *
'* : 4D Systems ULCD Goldelox or Picasso Graphic Processor *
'* : RFM69HCW the range will be approximatelly 1000 meters *
'**********************************************************************
' --------------------[ GPS Variables for NMEA sentenses ]---------------------/
' /
' $GPRMC,090045.000,A,3823.6645,N,02353.3600,E,0.02,195.80,170518,,,A*62 /
' $GNGGA,140405.000,3823.6010,N,02353.3054,E,1,9,0.88,0.8,M,35.9,M,,*40 /
' $GPGSA,A,3,18,08,10,11,14,27,22,32,01,,,,2.62,1.11,2.37*03 /
' $GPVTG,215.60,T,,M,0.44,N,0.82,K,A*37 /
' /
'-----------------------------------------------------------------------/
' When the GPS Module is POWERED ON, then the following sentenses are received.
' $PMTK011,MTKGPS*08
' $PMTK010,001*2E
' $PMTK010,002*2D
'*********************************************************************************
@ ERRORLEVEL -306 ; this command prevents the compiler to give you a notice of *
; crossing page boundary - make sure bits are set *
'*********************************************************************************
#IF __PROCESSOR__ = "18F26K22"
#CONFIG ; The PBP configuration for the PIC18F26K22 is:
; CONFIG FOSC = RCIO6 ; External RC oscillator
CONFIG FOSC = HSHP ; HS oscillator (high power > 16 MHz)
;*---------------------------------4x PLL ENABLE--------------------------------------*|
;* 4X PLL Enable *|
;* CONFIG PLLCFG = OFF ;Oscillator used directly *|
CONFIG PLLCFG = ON ;Oscillator multiplied by 4 *|
;*------------------------------------------------------------------------------------*|
;
; Primary clock enable bit
; CONFIG PRICLKEN = OFF ;Primary clock can be disabled by software
CONFIG PRICLKEN = ON ;Primary clock enabled
;
; Fail-Safe Clock Monitor Enable bit
CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled
; CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit
CONFIG IESO = OFF ;Oscillator Switchover mode disabled
; CONFIG IESO = ON ;Oscillator Switchover mode enabled
CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
;*--------------------------------------------------------------------------------------------------------;|
CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect ;|
CONFIG WDTPS = 32768 ; 1:32768 ---> HERE enable the watchdog timer with a 1:32768 postscale;|
;*--------------------------------------------------------------------------------------------------------;|
CONFIG PWRTEN = ON
CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status
CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Disabled
;*----------------------------------------------------------------------------------|
;*---------------Available configuration settings for PIC18F26K22-------------------|
;*----------------------------------------------------------------------------------|
;
; Oscillator Selection bits
; CONFIG FOSC = RC ;111X External RC oscillator, CLKOUT function on RA6
; CONFIG FOSC = ECLPIO6 ;EC oscillator (low power, <500 kHz)
; CONFIG FOSC = ECLP ;EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz)
; CONFIG FOSC = ECMPIO6 ;EC oscillator (medium power, 500 kHz-16 MHz)
; CONFIG FOSC = ECMP ;EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz)
; CONFIG FOSC = INTIO7 ;Internal oscillator block, CLKOUT function on OSC2
; CONFIG FOSC = INTIO67 ;Internal oscillator block
; CONFIG FOSC = RCIO6 ;External RC oscillator
; CONFIG FOSC = RC ;External RC oscillator, CLKOUT function on OSC2
; CONFIG FOSC = ECHPIO6 ;EC oscillator (high power, >16 MHz)
; CONFIG FOSC = ECHP ;EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
; CONFIG FOSC = HSMP ;HS oscillator (medium power 4-16 MHz)
; CONFIG FOSC = HSHP ;HS oscillator (high power > 16 MHz)
; CONFIG FOSC = XT ;XT oscillator
; CONFIG FOSC = LP ;LP oscillator
;*--------------------------------------------------------------------------------------------------------|
;* | -------------------------- | |
;* ----------------------------- | [PROTECTED OPTION FUSES] | ------------------------------------ |
;* | -------------------------- | |
;*--------------------------------------------------------------------------------------------------------|
CONFIG CP0 = OFF ; Block 0 (000800-003FFFh) not code-protected
CONFIG CP1 = OFF ; Block 1 (004000-007FFFh) not code-protected
CONFIG CP2 = OFF ; Block 2 (008000-00BFFFh) not code-protected
CONFIG CP3 = OFF ; Block 3 (00C000-00FFFFh) not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected
CONFIG CPD = OFF ; Data EEPROM not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-003FFFh) not write-protected
CONFIG WRT1 = OFF ; Block 1 (004000-007FFFh) not write-protected
CONFIG WRT2 = OFF ; Block 2 (008000-00BFFFh) not write-protected
CONFIG WRT3 = OFF ; Block 3 (00C000-00FFFFh) not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected
CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected
CONFIG WRTD = OFF ; Data EEPROM not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
CONFIG EBTR2 = OFF ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
CONFIG EBTR3 = OFF ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG
#ELSE
#MSG "Wrong Processor selected!"
#ENDIF
;*---------------------------------------------------------------------------------------------------------|
;*---------------------------------------------------------------------------------------------------------|
define OSC 64
INCLUDE "modedefs.bas"
INCLUDE "ALLDIGITAL.pbp"
'INCLUDE "DT_INTS-18.bas" ; Base Interrupt System
'INCLUDE "ReEnterPBP-18.bas" ; Include if using PBP interrupts
OSCCON = %01110000 ; 64Mhz
OSCTUNE.6 = 1 ; Enable 4x PLL
while ! osccon2.7 :WEND ; to make sure the pll has stabilised before you run any other code
'------------------------------------------------------------------------------|
' INITIALIZE RAM |
'------------------------------------------------------------------------------|
initialize:
CLEAR
'-------------------------------------------------------------------------------------------------------------------------------------------------------------
'***********************************************************************************************************
' --- NOTE --- *
'***********************************************************************************************************
' --------------- The following configuration will be set only for testing the RFM69HCW --------------------
'***********************************************************************************************************
' *
' when "0" then TRIS bit is set to output, while "1" TRIS bit is set to input *
' *
'***********************************************************************************************************
TRISA = %00000000 'use TRISA to specify which pin is (1 = input) and which (0 = output) (ALL pins are output or SPI configuration related)
TRISB = %00000000 'use TRISB to specify which pin is (1 = input) and which (0 = output) (RB7 PORTB.7 is the RX input pin of the EUART, the rest are output or SPI configuration related)
TRISC = %00010000 'use TRISC to specify which pin is (1 = input) and which (0 = output) (RC7 PORTC.7 is the RX input pin of the EUART, the rest are output or SPI configuration related)
'in PORTC the RC3 attached is an LED.
' The above comments may be different as the project includes more peripherals and we have configured the bits for each specific application.
'------------------------------------------------------------------------|
'--------------------------- TRIS A B C ---------------------------------|
'------------------------------------------------------------------------| RX2 TX2 SDO2 SDI2 SCK2 SS2 RX1 TX1 SDO1 SDI1
' OSC1 OSC2 SS1 | | | | | | | | | | |
' | | | | RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4
' PORTA.7 PORTA.6 PORTA.5 PORTA.4 PORTA.3 PORTA.2 PORTA.1 PORTA.0 | |28| |27| |26| |25| |24| |23| |22| |21| |20| |19| |18| |17| |16| |15|
' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 | ---------------------------------------------------------------------
' 0 0 0 0 0 0 0 0 | | |
'------------------------------------------------------------------------| | |
'------------------------------------------------------------------------| | |
' RX2 TX2 SDO2 SDI2 SCK2 SS2 | | |
' | | | | | | | | =============================== |
' PORTB.7 PORTB.6 PORTB.5 PORTB.4 PORTB.3 PORTB.2 PORTB.1 PORTB.0 | | | | |
' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 | | | PIC18F26K22 | |
' 0 0 0 0 0 0 0 0 | | | | |
'------------------------------------------------------------------------| | | | |
'------------------------------------------------------------------------| | =============================== |
' RX1 TX1 SDO1 SDI1 SCK1 | | |
' | | | | | | | |
' PORTC.7 PORTC.6 PORTC.5 PORTC.4 PORTC.3 PORTC.2 PORTC.1 PORTC.0 | | _ |
' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 | | |_| |
' 0 0 0 1 0 0 0 0 | | |
'------------------------------------------------------------------------| ---------------------------------------------------------------------
' |*1| |*2| |*3| |*4| |*5| |*6| |*7| |*8| |*9| |10| |11| |12| |13| |14|
'------------------------------------------------------------------------| RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3
'----------------------- At start all PORTS LOW -------------------------| | | | | |
' | MCLR SS1 OSC1 OSC2 SCK1
'------------------------------------------------------------------------|
PORTA = 0 'make low all ports at A range |
PORTB = 0 'make low all ports at B range |
PORTC = 0 'make low all ports at C range |
PORTE = 0 'make low all ports at E range |
'------------------------------------------------------------------------|
'------------------------------------------------------------------------|
'-------------------------- COMPARATORS OFF -----------------------------|
'------------------------------------------------------------------------|
CM1CON0.7 = 0 'Disable comparator1 |
CM2CON0.7 = 0 'Disable comparator2 |
'------------------------------------------------------------------------|
'************************************************************************
' *
' SPI CONFIGURATION REGISTERS *
' *
'************************************************************************
SSPCON1 = %00100010 ' in here we se the 5th bit of the SSPCON1 register and the last 4 bits for the clock speed at 64Mhz.
'bit 5 SSPxEN: Synchronous Serial Port Enable bit
'In both modes, when enabled, these pins must be properly configured as input or output
'In SPI mode:
'1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2)
'0 = Disables serial port and configures these pins as I/O port pins
'SSPxM<3:0>: Synchronous Serial Port Mode Select bits
'0000 = SPI Master mode, clock = FOSC/4
'0001 = SPI Master mode, clock = FOSC/16
'****************************************************************
'-----------------WE use the following setup--------------------*
'****************************************************************
' *
' 0010 = SPI Master mode, clock = FOSC/64 *
' *
'****************************************************************
'0011 = SPI Master mode, clock = TMR2 output/2
'0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
'0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
'1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))
SSP1STAT = %10000000 ' in here i need a help to understand what bits must be configured
'bit 7 SMP: SPI Data Input Sample bit
'SPI Master mode:
'1 = Input data sampled at end of data output time
'0 = Input data sampled at middle of data output time
'SPI Slave mode:
'SMP must be cleared when SPI is used in Slave mode
'bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
'In SPI Master or Slave mode:
'1 = Transmit occurs on transition from active to Idle clock state
'0 = Transmit occurs on transition from Idle to active clock state
'*-----------------------------------------------------------------------|
'*-----------------------------------------------------------------------|
CS1 VAR PORTA.5 ' chip select (SS) from PIC18F26K22 to RFM69HCW
SCK1 VAR PORTC.3 ' clock from PIC18F26K22 to RFM69HCW
SDI1 VAR PORTC.4 ' data IN , MISO from PIC18F26K22 to RFM69HCW
SDO1 VAR PORTC.5 ' data OUT, MOSI from PIC18F26K22 to RFM69HCW
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