SOLVED: How can I reduce ADC jitter

[Demon]

CONFIRMED: Noisy power definitely messes up everything when the PIC tries to compare the "wiper" reading with VDD/VSS, even using two 1K resistors to simulate 50% pot.

I switched to a 7805 supply and put back my "supposedly dirty" potentiometer. ADC low/high was back to a steady reading no matter where I turned the pot.

I had code prepared using the techniques discussed in Melanie's ADC thread (or was it SORT, I don't remember). I got lost looking at the computational feature of the ADC in the 16F18877; that could have replaced my averaging routine and most likely reduced time.

At worse if I get a dirty pot, I can drop the 1-2 lower bits from the 10-bit reading and still get 512-256 resolution out of a maximum 1024.

[Demon]

I did an extra test to confirm it wasn't another component on my main test board that was "messing up" the power.

I powered my isolated PIC with that DC-DC converter and sure enough ADC was jumping between 546 and 569 using my pot.

So now i have to find a 7805 variant that can supply 700mA without breaking a sweat.

[Ioannis]

Drift is tottaly different than jumping numbers...

When you said drift I assumed that you started with say 512 as a 50% of FSD and then it went up or down after some time, like 511, 510, 509 etc.

Having random numbers sure can be due to crappy and noisy Voltage on Vdd.

Ioannis